1. Field of the Invention
The present invention relates to a data processing device, a power supply voltage generator and method of controlling power supply voltage and more particularly, relates to a data processing device which has a regulator circuit, a supply voltage generator and method of controlling power supply voltage.
2. Description of Related Art
In recent years, semiconductors used in a mobile and other devices, saw an increased demand for a reduction in electrical power usage and a reduction in size. In the semiconductor device, the demands of the electrical power saving and the reduction in size also include the miniaturization of the production process. However, a power supply voltage in a system which includes a semiconductor device is 3V or 5V. Therefore, in the case where this type of power supply is used, it is difficult to save electrical power. One way to save electrical power in this type of system is by generating an internal voltage, which is lower than the power supply voltage used by the system, and using a regulator, or a similar device, and operating the internal circuit of the system by using the internal voltage.
However, output voltage of the regulator may change depending on an increase and decrease of consumption current (hereinafter referred to as “load current”) of the internal circuit. In the case where the output voltage of the regulator changes and the internal voltage becomes lower than the power supply voltage at which the internal circuit can function, there is a possibility that the internal circuit can malfunction. Therefore, in order to control the variation of the output voltage of the regulator, a capacitor for stability of the voltage, may be connected to the output of the regulator. Although a capacitance value of the capacitor is dependant on the fluctuating range of the load current, the capacitance value commonly becomes so large that the capacitor cannot be included in the semiconductor device. Because of this, the semiconductor device which is mounted in the regulator requires an additional terminal for connecting the capacitor and therefore other necessary terminals may not be created.
A related art power supply voltage variation suppressor, which suppresses a voltage variation by a load current change without depending on a capacitor for stability of the voltage, is disclosed in Japanese Unexamined Patent Application Publication No. 2000-305668 (Arai et al.). The power supply voltage variation suppressor disclosed in Arai et al. is shown in FIG. 14. In FIG. 14, CPU 109 switches from an operation state to a resting state based on a signal level of a stop clock signal which is input from a stop clock terminal 191. A load current Ic which is consumed by CPU 109 in the operating state is larger than in the resting state. A control circuit 120 controls a current value of current It which flows in a transistor 106 based on a current value control signal input to a current value control terminal 121. The control circuit 120 controls rate of change of transistor current It based on a time constant control signal input at the time constant control terminal 122.
FIG. 15 is a timing chart showing an operation of the power supply voltage variation suppressor 100. As shown in FIG. 15, CPU 109 is in the resting state when a stop clock signal level is low and is in the operating state when the stop clock signal level is high. Further, the current control signal level becomes low before and after the period during which the stop clock signal level is high (See, e.g., time t1-t4 and time t7 to t9). Furthermore, the time constant control signal includes a period in which the stop clock signal level is high and stays high longer than the period during which the stop clock signal level is high (time t3-t8). With respect to the transistor current It this current flows in the transistor 106 and increases gradually before the CPU current Ic consumed in CPU 109 increases, and decreases so as to counteract an increase of the CPU current Ic by controlling the stop clock signal, the current control signal and the time constant control signal as described above. Further the transistor current It also increases so as to counteract a decrease of the CPU current Ic, and may then gradually decrease.
In other words, the power voltage variation suppressor 100 prevents a rapid change in current flowing through CPU 109 from a power supply line 102 by using the transistor current It and also suppresses voltage variation of the power supply line 102. FIG. 16 shows a voltage waveform of a CPU terminal (a waveform of the power supply line 102) in the power voltage variation suppressor 100. As illustrated in FIG. 16, in the case where a power voltage variation suppressor 100 is not included, an overshoot and an undershoot occur in the voltage waveform depending on the switching of the operation state and the resting state, and a variation range of the power supply voltage increases. Conversely, where the power voltage variation suppressor 100 is included, it is possible to suppress a variation range of the power supply voltage to about half of the case where the power voltage variation suppressor (100) is not used.
Another related art Application, Japanese Unexamined Patent Application Publication No. 2006-285539 (Tadao Oshima) discloses a portable information reading device. The portable information reading device supplies additional load power, which a device needs, by using a second battery in addition to the first battery in the case where the load power of the device exceeds the available load power of the first battery.
The relationship between CPU current Ic and transistor current It in the power voltage variation suppressor 100 is shown in FIG. 17. As shown in FIG. 17, the power voltage variation suppressor 100 needs the transistor current It as well as the CPU current Ic. That is, the power voltage variation suppressor 100 disclosed in Arai et al. consumes transistor current It and leads to an increase in power consumption, which is a problem. The problem of increased power consumption is more notable in a system where the operating state and the resting state of the CPU 109 are switched frequently.